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A 0.5–9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With 1.25% UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling

The work

AuthorsF. Ahmad; G. Unruh; A. Iyer
Editors
Typemisc
Year2017
Also known asahmad20160595ghz, anon20160595ghz
Citekeyahmad2017fractionaln

Where it appeared

PublisherInstitute of Electrical and Electronics Engineers (IEEE)

How it got here

How it got hereagent via unpaywall
Added2026-10-27 18:52 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@misc{ahmad2017fractionaln,
  title        = {A 0.5–9.5-GHz, 1.2-µs Lock-Time Fractional-N DPLL With 1.25\% UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling},
  author       = {F. Ahmad and G. Unruh and A. Iyer},
  year         = {2017},
  publisher    = {Institute of Electrical and Electronics Engineers (IEEE)},
  doi          = {10.1109/jssc.2016.2626338},
}

This record lives at https://refs.drheap.org/ahmad2017fractionaln/ and will keep doing so. It used to be called ahmad20160595ghz, anon20160595ghz, and those addresses still resolve to this one.