Hyung‐Jin Lee
2 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.
A TDC-less ADPLL with 200-to-3200MHz range and 3mW power dissipation for mobile SoC clocking in 22nm CMOS
Nathaniel J. August and others (2012) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · Institute of Electrical and Electronics Engineers
A scalable sub-1.2mW 300MHz-to-1.5GHz host-clock PLL for system-on-chip in 32nm CMOS
Hyung‐Jin Lee and others (2011) · Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference · Institute of Electrical and Electronics Engineers