Luca Benini

9 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET

Gianna Paulin and others (2024) · 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) · IEEE

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS

Paul Scheffler and others (2024)

Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor

Riccardo Tedeschi and others (2024) · WiPiEC Journal - Works in Progress in Embedded Computing Journal

HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing

Andreas Kurth and others (2022) · IEEE Transactions on Parallel and Distributed Systems · Institute of Electrical and Electronics Engineers

Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes

Pasquale Davide Schiavone and others (2021) · Institute of Electrical and Electronics Engineers (IEEE)

Manticore: A 4096-Core RISC-V Chiplet Architecture for Ultraefficient Floating-Point Computing

Florian Zaruba and others (2021) · IEEE Micro · Institute of Electrical and Electronics Engineers

BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research

Jonathan Balkind and others (2020) · International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)

LLHD: a multi-level intermediate representation for hardware description languages

Fabian Schuiki and others (2020) · Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

Andreas Kurth and others (2017) · arXiv (Cornell University) · Cornell University