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Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET

The work

AuthorsGianna Paulin; Paul Scheffler; Thomas Benz; Matheus Cavalcante; Tim Fischer; Manuel Eggimann; Yichao Zhang; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; Davide Rossi; Luca Benini
Editors
Typeinproceedings
Year2024
Citekeypaulin2024occamy

Where it appeared

Published in2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
PublisherIEEE
Pages1--2

Identifiers

DOI10.1109/vlsitechnologyandcir46783.2024.10631529

Access

Landing pagehttps://doi.org/10.1109/vlsitechnologyandcir46783.2024.10631529

How it got here

How it got hereagent via crossref
Added2026-10-27 07:19 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@inproceedings{paulin2024occamy,
  title        = {Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83\% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET},
  author       = {Gianna Paulin and Paul Scheffler and Thomas Benz and Matheus Cavalcante and Tim Fischer and Manuel Eggimann and Yichao Zhang and Nils Wistoff and Luca Bertaccini and Luca Colagrande and Gianmarco Ottavi and Frank K. Gürkaynak and Davide Rossi and Luca Benini},
  year         = {2024},
  booktitle    = {2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)},
  publisher    = {IEEE},
  pages        = {1--2},
  doi          = {10.1109/vlsitechnologyandcir46783.2024.10631529},
}

This record lives at https://refs.drheap.org/paulin2024occamy/ and will keep doing so.