M. Litterick

2 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

Full flow clock domain crossing - from source to si

M. Litterick (2016) · DVCON

Pragmatic simulation-based verification of clock domain crossing signals and jitter using SystemVerilog Assertions

M. Litterick (2006) · DVCON