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Pragmatic simulation-based verification of clock domain crossing signals and jitter using SystemVerilog Assertions
The work
| Authors | M. Litterick |
|---|---|
| Editors | |
| Type | inproceedings |
| Year | 2006 |
| Citekey | litterick2006pragmatic |
Where it appeared
| Published in | DVCON |
|---|
How it got here
| How it got here | agent via bibtex |
|---|---|
| Added | 2026-10-26 03:23 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Filed under
Cite it as
@inproceedings{litterick2006pragmatic,
title = {Pragmatic simulation-based verification of clock domain crossing signals and jitter using SystemVerilog Assertions},
author = {M. Litterick},
year = {2006},
booktitle = {DVCON},
}
This record lives at https://refs.drheap.org/litterick2006pragmatic/ and will keep doing so.