M. Valencia

3 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

Logic-Timing Simulation and the Degradation Delay Model

M. J. Bellido-Díaz and others (2005) · Imperial College Press

Logical modelling of delay degradation effect in static CMOS gates

M. J. Bellido-Díaz and others (2000) · Institution of Engineering and Technology (IET)

Degradation Delay Model Extension to CMOS Gates

J. Juan-Chico and others (2000) · Springer Berlin Heidelberg