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Logical modelling of delay degradation effect in static CMOS gates
The work
| Authors | M. J. Bellido-Díaz; J. Juan-Chico; A. Acosta; M. Valencia; J. L. Huertas |
|---|---|
| Editors | |
| Type | misc |
| Year | 2000 |
| Also known as | anon2000logical |
| Citekey | bellidodiaz2000logical |
Where it appeared
| Publisher | Institution of Engineering and Technology (IET) |
|---|
Identifiers
| DOI | 10.1049/ip-cds:20000197 |
|---|
How it got here
| How it got here | agent via unpaywall |
|---|---|
| Added | 2026-10-23 09:47 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{bellidodiaz2000logical,
title = {Logical modelling of delay degradation effect in static CMOS gates},
author = {M. J. Bellido-Díaz and J. Juan-Chico and A. Acosta and M. Valencia and J. L. Huertas},
year = {2000},
publisher = {Institution of Engineering and Technology (IET)},
doi = {10.1049/ip-cds:20000197},
}
This record lives at https://refs.drheap.org/bellidodiaz2000logical/ and will keep
doing so. It used to be called anon2000logical, and those addresses still resolve to this one.