Marc Renaudin

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Marc Renaudin

Marc Renaudin, Grenoble (TIMA): asynchronous and quasi-delay-insensitive circuits, from DPA-resistant design in 2005 to model checking and LNT/CADP modelling of asynchronous circuits. Three records, 2005-2020.

Modeling an Asynchronous Circuit Dedicated to the Protection Against Physical Attacks

Radu Mateescu and others (2020) · Electronic Proceedings in Theoretical Computer Science · Open Publishing Association

Model-checking Synthesizable SystemVerilog Descriptions of Asynchronous Circuits

Aymane Bouzafour and others (2018) · 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) · IEEE

DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

Ghislain Fraidy Bouesse and others (2005) · Design, Automation and Test in Europe (DATE 2005)