DPA on quasi delay insensitive asynchronous circuits: formalization and improvement

The work

AuthorsGhislain Fraidy Bouesse; Marc Renaudin; S. Dumont; F. Germain
Editors
Typeinproceedings
Year2005
Citekeybouesse2005dpa

Where it appeared

Published inDesign, Automation and Test in Europe (DATE 2005)
Pages424--429

Identifiers

DOI10.1109/date.2005.124

Access

Landing pagehttps://hal.science/hal-00009567

Related

Distinct fromsimoes2023lowlatency

From bibtex.

Abstract

The purpose of this paper is to formally specify a flow devoted to the design of Differential Power Analysis (DPA) resistant QDI asynchronous circuits. The paper first proposes a formal modeling of the electrical signature of QDI asynchronous circuits. The DPA is then applied to the formal model in order to identify the source of leakage of this type of circuits. Finally, a complete design flow is specified to minimize the information leakage. The relevancy and efficiency of the approach is demonstrated using the design of an AES crypto-processor.

A copy is held

pdf, 579.2 kB. Not published — it may be under copyright. The facts and links here are.

How it got here

How it got hereagent via bibtex
Added2026-09-17 10:15 UTC
Approved bya person 2026-09-17 16:52 UTC

Filed under

hardware-security renaudin the-cost-is-in-the-translation the-switch-or-the-curve

Cite it as

@inproceedings{bouesse2005dpa,
  title        = {DPA on quasi delay insensitive asynchronous circuits: formalization and improvement},
  author       = {Ghislain Fraidy Bouesse and Marc Renaudin and S. Dumont and F. Germain},
  year         = {2005},
  booktitle    = {Design, Automation and Test in Europe (DATE 2005)},
  pages        = {424--429},
  doi          = {10.1109/date.2005.124},
}

This record lives at https://refs.drheap.org/bouesse2005dpa/ and will keep doing so.