Peter A. Beerel

2 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

Generalizable Verilog Modeling Framework for Synchronous and Asynchronous Superconducting Pulse-Based Logic Gates

Elisabeth Feng and others (2026)

Proteus: An ASIC Flow for GHz Asynchronous Designs

Peter A. Beerel and others (2011) · IEEE Design & Test of Computers · Institute of Electrical and Electronics Engineers