Proteus: An ASIC Flow for GHz Asynchronous Designs
The work
| Authors | Peter A. Beerel; Georgios D. Dimou; Andrew Lines |
|---|---|
| Editors | |
| Type | article |
| Year | 2011 |
| Citekey | beerel2011proteus |
Where it appeared
| Published in | IEEE Design & Test of Computers |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Volume | 28 |
| Issue | 5 |
| Pages | 36--51 |
Identifiers
| DOI | 10.1109/mdt.2011.114 |
|---|---|
| OpenAlex | W2097453879 |
Access
| Landing page | https://doi.org/10.1109/mdt.2011.114 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
Editors' note:The high-performance benefits of asynchronous design have hitherto been obtained only using full-custom design. This article presents an industrial-strength asynchronous ASIC CAD flow that enables the automatic synthesis and physical design of high-level specifications into GHz silicon, greatly reducing design time and enabling far wider use of asynchronous technology.—Montek Singh (UNC Chapel Hill) and Luciano Lavagno (Politecnico di Torino)
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-25 21:44 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{beerel2011proteus,
title = {Proteus: An ASIC Flow for GHz Asynchronous Designs},
author = {Peter A. Beerel and Georgios D. Dimou and Andrew Lines},
year = {2011},
journal = {IEEE Design \& Test of Computers},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {28},
number = {5},
pages = {36--51},
doi = {10.1109/mdt.2011.114},
}
This record lives at https://refs.drheap.org/beerel2011proteus/ and will keep doing so.