More states per device

A subject the papers are about. The loosest grouping, and the one to reach for last.

Getting more than two states out of one device, and what that costs. Collects the multi-valued-logic designs together with the machine that tried it in 1959, so the modern circuits can be read against the one that was actually built and abandoned. Membership requires the work to implement or assess more states per device; a paper about the underlying material belongs in the fabrication sets instead.

The set now reaches up the stack as well as across the device. Setun is a working ternary computer; the CNTFET papers are ternary logic at the gate and circuit level; and Srinivasu and Sridharan's multi-digit adders are what you build once you have those gates -- the level where a radix change either pays or does not, because a ternary digit carries log2(3) bits and so needs fewer carry stages for the same range.

One caution for reading the modern members together. Setun's numbers are measurements of a machine that existed. Everything since is HSPICE simulation over compact device models, and the power-delay percentages are claims about a simulator rather than about silicon. Nothing in those papers misrepresents this, but the contrast with Setun is the most useful thing the set offers and it is easy to miss.