FRAIGs: A Unifying Representation for Logic Synthesis and Verification
The work
| Authors | Alan Mishchenko; Satrajit Chatterjee; Roland Jiang; Robert Brayton |
|---|---|
| Editors | |
| Type | techreport |
| Year | 2005 |
| Citekey | mishchenko2005fraigs |
Where it appeared
| Publisher | EECS Department, University of California, Berkeley |
|---|---|
| School | EECS Department, University of California, Berkeley |
Access
| Landing page | https://embedded.eecs.berkeley.edu/mvsis/doc/2004/fraigs.pdf |
|---|
Empty on purpose
| doi |
Related
| Distinct from | bradley2011satbased |
|---|---|
| Distinct from | bryant1986graphbased |
| Distinct from | dai2026guarded |
| Distinct from | davis2013verified |
| Distinct from | een2011efficient |
| Distinct from | kaufmann2024extracting |
| Distinct from | seufert2026certified |
| Distinct from | yang2025forword |
| Distinct from | yin2025boole |
| Distinct from | yu2025fraigbmc |
| Distinct from | zhang2025fastlec |
From bibtex.
Abstract
AND-INV graphs (AIGs) are Boolean networks composed of two-input AND-gates and inverters. In the known applications, such as equivalence checking and technology mapping, AIGs are used to represent and manipulate Boolean functions. AIGs powered by simulation and Boolean satisfiability lead to functionally reduced AIGs (FRAIGs), which are semi-canonical in the sense that each FRAIG node has unique functionality among all the nodes currently present in the FRAIG. The paper shows that FRAIGs can be used to unify and enhance many phases of logic synthesis: from the representation of the original and the intermediate netlists derived by logic optimization, through technology mapping over multiple logic structures, to combinational equivalence checking. Experimental results on large public benchmarks confirm the practicality of using FRAIGs throughout the logic synthesis flow.
A copy is held
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How it got here
| How it got here | agent via bibtex |
|---|---|
| Added | 2026-09-16 19:13 UTC |
| Approved by | a person 2026-09-16 20:46 UTC |
Filed under
Cite it as
@techreport{mishchenko2005fraigs,
title = {FRAIGs: A Unifying Representation for Logic Synthesis and Verification},
author = {Alan Mishchenko and Satrajit Chatterjee and Roland Jiang and Robert Brayton},
year = {2005},
publisher = {EECS Department, University of California, Berkeley},
school = {EECS Department, University of California, Berkeley},
}
This record lives at https://refs.drheap.org/mishchenko2005fraigs/ and will keep doing so.