Pre-Silicon DFT Verification on SOC Slim Model

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Abstract

Pre-Silicon verification test run times in SOC models are long. Pre-Silicon DFT verification tests are especially longer. A slim model was developed which had selected RTL components and the rest substituted by Bus Functional Models (BFM) to help reduce simulation runtime. Connectivity of DFT network in this slim model with stubbed out components wasn't complete. We connected the DFT signals through forces, which formed a continuous chain from the top level ring, down to each of the child rings and back to the top level ring. This model helped us to validate most of the DFT features so that only critical features were left to be validated in the full model. Build and runtimes were shorter for this model compared to the full model. We wrote directed tests to validate the RTL components present in the slim model and were able to run/debug issues faster. This model was widely used by the DFT team for multiple project milestones providing us huge savings in the simulation runtime and debug time.