A 0.009 mm2 Wide-Tuning Range Automatically Placed-and-Routed ADPLL in 14-nm FinFET CMOS
The work
| Authors | David M. Moore; Thucydides Xanthopoulos; Scott Meninger; David D. Wentzloff |
|---|---|
| Editors | |
| Type | article |
| Year | 2018 |
| Citekey | moore20180009 |
Where it appeared
| Published in | IEEE Solid-State Circuits Letters |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Volume | 1 |
| Issue | 3 |
| Pages | 74--77 |
Identifiers
| DOI | 10.1109/lssc.2018.2827880 |
|---|---|
| OpenAlex | W2801898480 |
Access
| Landing page | https://doi.org/10.1109/lssc.2018.2827880 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
An automatically placed-and-routed all-digital PLL for high-performance clock generation and distribution in many-core processors is presented. The proposed design leverages a phase domain architecture, and features an embedded TDC constructed from standard cells. TDC resolution is enhanced through the use of a phase interpolator. The standard cell library is extended with custom oscillator cells are designed to achieve optimized power, performance, and area. Timing and handling of potentially metastable paths is additionally handled by the digital design How. The clock generator has been fabricated in a 14-nm FinFET process, and occupies an area of 0.009 mm2. The design features a tuning range from 1.0 to 5.5 GHz (80%). Output period jitter of 1.29 ps is achieved with a power consumption of 9.7 mW.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-27 18:41 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{moore20180009,
title = {A 0.009 mm2 Wide-Tuning Range Automatically Placed-and-Routed ADPLL in 14-nm FinFET CMOS},
author = {David M. Moore and Thucydides Xanthopoulos and Scott Meninger and David D. Wentzloff},
year = {2018},
journal = {IEEE Solid-State Circuits Letters},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {1},
number = {3},
pages = {74--77},
doi = {10.1109/lssc.2018.2827880},
}
This record lives at https://refs.drheap.org/moore20180009/ and will keep doing so.