A Hierarchical Analysis of Propositional Temporal Logic Based on Intervals

From bibtex.

Abstract

We present a hierarchical framework for analysing propositional linear-time temporal logic (PTL) to obtain standard results such as a small model property, decision procedures and axiomatic completeness. Both finite time and infinite time are considered and one consequent benefit of the framework is the ability to systematically reduce infinite-time reasoning to finite-time reasoning. The treatment of PTL with both the operator until and past time naturally reduces to that for PTL without either one. Our method utilises a low-level normal form for PTL called a transition configuration. In addition, we employ reasoning about intervals of time. Besides being hierarchical and interval-based, the approach differs from other analyses of PTL typically based on sets of formulas and sequences of such sets. Instead we describe models using time intervals represented as finite and infinite sequences of states. The analysis relates larger intervals with smaller ones. Steps involved are expressed in Propositional Interval Temporal Logic (PITL) which is better suited than PTL for sequentially combining and decomposing formulas. Consequently, we can articulate issues in PTL model construction of equal relevance in more conventional analyses but normally only considered at the metalevel. We also describe a decision procedure based on Binary Decision Diagrams. Beyond the specific issues involving PTL, the research is a significant application of ITL and interval-based reasoning and illustrates a general approach to formally reasoning about sequential and parallel behaviour in discrete linear time. The work also includes some interesting representation theorems. In addition, it has relevance to hardware description and verification since the specification languages PSL/Sugar (now IEEE standard 1850) and 'temporal e' (part of IEEE candidate standard 1647) both contain temporal constructs concerning intervals of time as does the related SystemVerilog Assertion language contained in SystemVerilog, an extension of the IEEE 1364-2001 Verilog language.