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Measuring architectural vulnerability factors

The work

AuthorsShubhendu S. Mukherjee; Christopher T. Weaver; Joel Emer; S.K. Reinhardt; T. Austin
Editors
Typearticle
Year2003
Citekeymukherjee2003measuring

Where it appeared

Published inIEEE Micro
PublisherInstitute of Electrical and Electronics Engineers
Volume23
Issue6
Pages70--75

Identifiers

DOI10.1109/mm.2003.1261389
OpenAlexW2047171058

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

The continuous exponential growth in transistors per chip as described by Moore's law has spurred tremendous progress in the functionality and performance of semiconductor devices, particularly microprocessors. At the same time, each succeeding technology generation has introduced new obstacles to maintaining this growth rate. Transient faults caused by single-event upsets have emerged as a key challenge likely to gain significantly more importance in the next few design generations. Techniques for dealing with these faults exist, but they come at a cost. Designers need accurate soft-error estimates early in the design cycle to weigh the benefits of error protection techniques against their costs. This article presents a method for generating these estimates.

How it got here

How it got hereagent via openalex
Added2026-10-26 14:41 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@article{mukherjee2003measuring,
  title        = {Measuring architectural vulnerability factors},
  author       = {Shubhendu S. Mukherjee and Christopher T. Weaver and Joel Emer and S.K. Reinhardt and T. Austin},
  year         = {2003},
  journal      = {IEEE Micro},
  publisher    = {Institute of Electrical and Electronics Engineers},
  volume       = {23},
  number       = {6},
  pages        = {70--75},
  doi          = {10.1109/mm.2003.1261389},
}

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