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Hardware Verification Using Software Analyzers

The work

AuthorsRajdeep Mukherjee; Daniel Kroening; Tom Melham
Editors
Typemisc
Year2015
Citekeymukherjee2015hardware

Where it appeared

Published inIEEE Computer Society Annual Symposium on VLSI
Pages7--12

Identifiers

DOI10.1109/isvlsi.2015.107
OpenAlexW1917325995

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

Program analysis is a highly active area of research, and the capacity and precision of software analyzers is improving rapidly. We investigate the use of modern software verification tools for formal property checking of hardware given in Verilog at register-transfer level. To this end, we translate RTL Verilog into an equivalent word-level ANSI-C program, according to synthesis semantics. The property of interest is instrumented into the Cprogram as an assertion. We subsequently apply three different software verification techniques -- bounded model checking, path-based symbolic simulation and abstract interpretation -- and compare their performance to conventional methods for property verification of hardware designs at net list and register transfer level. Our experimental results indicate that speedups of more than an order of magnitude are possible. To the best of our knowledge, this is the first attempt to perform property verification of hardware IPs given at register-transfer level using software verifiers.

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Added2026-10-24 21:36 UTC
Not denied bya person 2026-10-29 17:12 UTC

Filed under

melham

Cite it as

@misc{mukherjee2015hardware,
  title        = {Hardware Verification Using Software Analyzers},
  author       = {Rajdeep Mukherjee and Daniel Kroening and Tom Melham},
  year         = {2015},
  journal      = {IEEE Computer Society Annual Symposium on VLSI},
  pages        = {7--12},
  doi          = {10.1109/isvlsi.2015.107},
}

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