An experimental 1.5-V 64-Mb DRAM
The work
| Authors | Y. Nakagome; Hiroki Tanaka; K. Takeuchi; E. Kume; Yoshio Watanabe; T. Kaga; Y. Kawamoto; F. Murai; R. Izawa; Digh Hisamoto; T. Kisu; Takashi Nishida; E. Takeda; K. Itoh |
|---|---|
| Editors | |
| Type | article |
| Year | 1991 |
| Citekey | nakagome1991experimental |
Where it appeared
| Published in | IEEE Journal of Solid-State Circuits |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Volume | 26 |
| Issue | 4 |
| Pages | 465--472 |
Identifiers
| DOI | 10.1109/4.75040 |
|---|---|
| OpenAlex | W2128231633 |
Access
| Landing page | https://doi.org/10.1109/4.75040 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 mu m/sup 2/ crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 mu m electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs.>
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-27 18:37 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{nakagome1991experimental,
title = {An experimental 1.5-V 64-Mb DRAM},
author = {Y. Nakagome and Hiroki Tanaka and K. Takeuchi and E. Kume and Yoshio Watanabe and T. Kaga and Y. Kawamoto and F. Murai and R. Izawa and Digh Hisamoto and T. Kisu and Takashi Nishida and E. Takeda and K. Itoh},
year = {1991},
journal = {IEEE Journal of Solid-State Circuits},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {26},
number = {4},
pages = {465--472},
doi = {10.1109/4.75040},
}
This record lives at https://refs.drheap.org/nakagome1991experimental/ and will keep doing so.