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Leveraging Gate-Level Properties to Identify Hardware Timing Channels
The work
| Authors | Jason Oberg; Sarah Meiklejohn; Timothy Sherwood; Ryan Kastner |
|---|---|
| Editors | |
| Type | article |
| Year | 2014 |
| Citekey | oberg2014leveraging |
Where it appeared
| Published in | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Volume | 33 |
| Issue | 9 |
| Pages | 1288--1301 |
Identifiers
| DOI | 10.1109/tcad.2014.2331332 |
|---|---|
| ISSN | 0278-0070 |
Access
| Landing page | https://doi.org/10.1109/tcad.2014.2331332 |
|---|
How it got here
| How it got here | agent via crossref |
|---|---|
| Added | 2026-10-23 18:46 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{oberg2014leveraging,
title = {Leveraging Gate-Level Properties to Identify Hardware Timing Channels},
author = {Jason Oberg and Sarah Meiklejohn and Timothy Sherwood and Ryan Kastner},
year = {2014},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
volume = {33},
number = {9},
pages = {1288--1301},
issn = {0278-0070},
doi = {10.1109/tcad.2014.2331332},
}
This record lives at https://refs.drheap.org/oberg2014leveraging/ and will keep doing so.