DFiant: A dataflow hardware description language

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Abstract

Today's dominant hardware description languages (HDLs), namely Verilog and VHDL, tightly couple design functionality with timing requirements and target device constraints. As hardware designs and device architectures became increasingly more complex, these dominant HDLs yield verbose and unportable code. To raise the level of abstraction, several high-level synthesis (HLS) tools were introduced, usually based on software languages such as C++. Unfortunately, designing with sequential software language constructs comes with a price; the designer loses the ability to control hardware construction and data scheduling, which is crucial in many design use-cases. In this paper, we introduce DFiant, a Scala-based HDL that uses the dataflow model to decouple functionality from implementation constraints. DFiant's frontend enables functional bit-accurate dataflow programming, while maintaining a complete timing-agnostic and device-agnostic code. DFiant bridges the gap between software programming and hardware construction, driving an intuitive functional object oriented code into a highperformance hardware implementation.