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Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction

The work

AuthorsArash Saifhashemi; Hossein Pedram
Editors
Typemisc
Year2003
Also known assaifhashemi2004verilog
Citekeysaifhashemi2003verilog

Where it appeared

Published inProceedings - ACM IEEE Design Automation Conference
PublisherAssociation for Computing Machinery

Identifiers

DOI10.1109/dac.2003.1219018
OpenAlexW4246920838

Access

Landing pagehttps://doi.org/10.1109/dac.2003.1219018

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

In this paper, we show how to use Verilog HDL along with PLI (Programming Language Interface) to model asynchronous circuits at the behavioral level by implementing CSP (Communicating Sequential Processes) language constructs. Channels and communicating actions are modeled in Verilog HDL as abstract actions.

How it got here

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Added2026-10-25 22:45 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@misc{saifhashemi2003verilog,
  title        = {Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction},
  author       = {Arash Saifhashemi and Hossein Pedram},
  year         = {2003},
  journal      = {Proceedings - ACM IEEE Design Automation Conference},
  publisher    = {Association for Computing Machinery},
  doi          = {10.1109/dac.2003.1219018},
}

This record lives at https://refs.drheap.org/saifhashemi2003verilog/ and will keep doing so. It used to be called saifhashemi2004verilog, and those addresses still resolve to this one.