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Abstract
Faults attacks are a powerful tool to break some implementations of robust cryptographic algorithms such as AES and DES. Various methods of faults attack on cryptographic systems have been discovered and researched. However, to the authors' knowledge, all the attacks published so far use a theoretical model of faults. In this paper we prove that we are able to reproduce experimentally the random errors model used by G. Piret and J.J. Quisquater (2003) to realize practical fault attack on a smart card embedding an AES encryptor by under-powering it. In spite of the fact that this method is a convenient fault injection technique to set up, it does not often appear in the open literature. We argue that the fault model is consistent with a setup violation: errors appear at the end of combinatorial logic cones, caused by an early sampling in the downwards registers. We also carry out an extensive characterization of the faults, in terms of spatial and temporal localization.
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Cite it as
@misc{selmane2008practical,
title = {Practical Setup Time Violation Attacks on AES},
author = {Nidhal Selmane and Sylvain Guilley and Jean‐Luc Danger},
year = {2008},
journal = {European Dependable Computing Conference},
pages = {91--96},
doi = {10.1109/edcc-7.2008.11},
}