The bibliographic entry was discovered and compiled by a machine, and published without a person checking it against the publication. The publication itself is the authors' own work — this badge says nothing about it.
Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs
From OpenAlex, which stores abstracts as an
index of words and their positions: what is shown is rebuilt from that,
and reads fluently whether or not it is what the author wrote.
Abstract
This paper introduces a fully free and open source software (FOSS) architecture-neutral FPGA framework comprising of Yosys for Verilog synthesis, and nextpnr for placement, routing, and bitstream generation. Currently, this flow supports two commercially available FPGA families, Lattice iCE40 (up to 8K logic elements) and Lattice ECP5 (up to 85K elements) and has been hardware-proven for custom-computing machines including a low-power neural-network accelerator and an OpenRISC system-on-chip capable of booting Linux. Both Yosys and nextpnr have been engineered in a highly flexible manner to support many of the features present in modern FPGAs by separating architecture-specific details from the common mapping algorithms.This framework is demonstrated on a longest-path case study to find an atypical single source-sink path occupying up to 45% of all on-chip wiring.
How it got here
How it got here
agent via openalex
Added
2026-10-25 00:15 UTC
Not denied by
a person 2026-10-29 17:12 UTC
Cite it as
@misc{shah2019yosysnextpnr,
title = {Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs},
author = {David Shah and Eddie Hung and Clifford Wolf and Serge Bazanski and Dan Gisselquist and Miodrag Milanović},
year = {2019},
journal = {IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)},
pages = {1--4},
doi = {10.1109/fccm.2019.00010},
}