The bibliographic entry was discovered and compiled by a machine, and published without a person checking it against the publication. The publication itself is the authors' own work — this badge says nothing about it.
Modeling the effect of technology trends on the soft error rate of combinational logic
From OpenAlex, which stores abstracts as an
index of words and their positions: what is shown is rebuilt from that,
and reads fluently whether or not it is what the author wrote.
Abstract
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to-end model that enables us to compute the soft error rates (SER) for existing and future microprocessor-style designs. The model captures the effects of two important masking phenomena, electrical masking and latching-window masking, which inhibit soft errors in combinational logic. We quantify the SER due to high-energy neutrons in SRAM cells, latches, and logic circuits for feature sizes from 600 nm to 50 nm and clock periods from 16 to 6 fan-out-of-4 inverter delays. Our model predicts that the SER per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements. Our result emphasizes that computer system designers must address the risks of soft errors in logic circuits for future designs.
How it got here
How it got here
agent via openalex
Added
2026-10-25 23:43 UTC
Not denied by
a person 2026-10-29 17:12 UTC
Cite it as
@misc{shivakumar2002modeling,
title = {Modeling the effect of technology trends on the soft error rate of combinational logic},
author = {Premkishore Shivakumar and Michael Kistler and Stephen W. Keckler and Doug Burger and Lorenzo Alvisi},
year = {2002},
journal = {IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)},
pages = {389--398},
doi = {10.1109/dsn.2002.1028924},
}