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Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip

The work

AuthorsVishnu Srinivasan; K. J. Ray Liu
Editors
Typemisc
Year1994
Citekeysrinivasan1994full

Where it appeared

Published inProceedings - International Conference on Image Processing
PublisherInstitute of Electrical and Electronics Engineers
Pages606-610 vol.3

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Abstract

Presents a full-custom VLSI design of high-speed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been implemented to demonstrate its performance. The authors show that the VLSI implementation of this class of DCT/IDCT algorithms can easily meet the high-speed requirements of HDTV due to its modularity, regularity, local connectivity, and scalability. The design of the 8×8 DCT/IDCT can operate at 50 MHz with a 400 Mbps throughput based on a very conservative estimate under 1.2μ CMOS technology.

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Cite it as

@misc{srinivasan1994full,
  title        = {Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip},
  author       = {Vishnu Srinivasan and K. J. Ray Liu},
  year         = {1994},
  journal      = {Proceedings - International Conference on Image Processing},
  publisher    = {Institute of Electrical and Electronics Engineers},
  pages        = {606-610 vol.3},
  doi          = {10.1109/icip.1994.413734},
}

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