SystemC transaction level models and RTL verification
The work
| Authors | Stuart Swan |
|---|---|
| Editors | |
| Type | misc |
| Year | 2006 |
| Citekey | swan2006systemc |
Where it appeared
| Published in | Proceedings - ACM IEEE Design Automation Conference |
|---|---|
| Publisher | Association for Computing Machinery |
| Pages | 90 |
Identifiers
| DOI | 10.1145/1146909.1146937 |
|---|---|
| OpenAlex | W2097331811 |
Access
| Landing page | https://doi.org/10.1145/1146909.1146937 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are being reused for RTL verification. The paper discusses how the task of system verification is changing as systems become more complex and it discusses how companies are striving to eliminate fragmentation within their design and verification flows by leveraging SystemC transaction level models.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-24 21:37 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{swan2006systemc,
title = {SystemC transaction level models and RTL verification},
author = {Stuart Swan},
year = {2006},
journal = {Proceedings - ACM IEEE Design Automation Conference},
publisher = {Association for Computing Machinery},
pages = {90},
doi = {10.1145/1146909.1146937},
}
This record lives at https://refs.drheap.org/swan2006systemc/ and will keep doing so.