Simulation Tools for Digital LSI Design

From bibtex.

Abstract

This thesis proposes a timing simulator (RSIM) based on a uniquely simple transistor model. RSIM allows a designer to determine both the functional and approximate timing characteristics of a MOS network with more accuracy than gate-level simulation, and using larger circuits than are accommodated by circuit analysis programs. In RSIM, transistors are modeled as resistors; the logic states of a transistor's terminal nodes determine its effective resistance. Using this model, a MOS network is simulated as a network of resistors where each node's value is determined by the resistance of its connections to various inputs. Transition times are detennined from the RC time constant calculated for the node by examining the surrounding network; (R from the transistors, C from the interconnect and gate capacitance). The network's behavior as inputs are given values is calculated by an efficient event-driven algorithm. Two changes to the underlying model are also investigated: (1) further simplifying the transistor model to an on/off switch (which can be thought of as a degenerate resistor). Several approaches to switch-level simulation are developed, one particularly well-suited for implementation using parallel hardware. (2) modeling the behavior of a network of switches by a system of logic equations. Various compilation strategies are evaluated for producing code that implements the system of equations. Name and Title of Thesis Supervisor: Stephen A. Ward, Associate Professor of Computer Science an4 Engineering Key Words and Phrases: circuit simulation, logic simulation, timing analysis, CAD tools -3- ACKNOWLEDGMENTS Thanks everybody: Steve Ward Ron Rivest Gerry Sussman Bert Halstead Clark Baker and the rest of RTS, past and present Mark Johnson Dave Gross Jeff Fox Bob Yodlowski Doug Williams Debbie Cohn The good advice, kind words, insight, and support provided over the years by these fine folks, and others, have made this thesis possible.