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Abstract
The matrix transposition operation is a necessary step in several image/video compression and decompression algorithms, in particular the discrete cosine transform (DCT) and its inverse (IDCT), and some distributed arithmetic applications. These algorithms have to be performed at high data-rates, and with a minimum of power dissipation for portable applications. The authors describe how the clocked solution is usually implemented, and present two new asynchronous architectures that perform matrix transposition. These architectures, one based on two phase signaling, one based on four phase signaling, have better characteristics than the clocked solution in terms of latency and power, at no cost in area or throughput. They discuss the characteristics of these three architectures and evaluate the relative advantages of each one.
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Cite it as
@misc{tierno1997asynchronous,
title = {Asynchronous transpose-matrix architectures},
author = {J. Tierno and Prabhakar N. Kudva},
year = {1997},
journal = {IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD)},
publisher = {Institute of Electrical and Electronics Engineers},
pages = {423--428},
doi = {10.1109/iccd.1997.628904},
}