An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS
The work
| Authors | Sriram R. Vangal; Jason Howard; Greg Ruhl; Saurabh Dighe; H. Wilson; James W. Tschanz; David Finan; A. Singh; Tiju Jacob; S. Jain; Vasantha Erraguntla; Clark Roberts; Yatin Hoskote; Nitin Borkar; Shekhar Y. Borkar |
|---|---|
| Editors | |
| Type | article |
| Year | 2008 |
| Citekey | vangal200880tile |
Where it appeared
| Published in | IEEE Journal of Solid-State Circuits |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Volume | 43 |
| Issue | 1 |
| Pages | 29--41 |
Identifiers
| DOI | 10.1109/jssc.2007.910957 |
|---|---|
| OpenAlex | W2159747318 |
Access
| Landing page | https://doi.org/10.1109/jssc.2007.910957 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined single-precision floating-point multiply accumulators (FPMAC) which feature a single-cycle accumulation loop for high throughput. The on-chip 2-D mesh network provides a bisection bandwidth of 2 Terabits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm2custom design contains 100 M transistors. The fully functional first silicon achieves over 1.0 TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07 V supply.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-24 21:29 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{vangal200880tile,
title = {An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS},
author = {Sriram R. Vangal and Jason Howard and Greg Ruhl and Saurabh Dighe and H. Wilson and James W. Tschanz and David Finan and A. Singh and Tiju Jacob and S. Jain and Vasantha Erraguntla and Clark Roberts and Yatin Hoskote and Nitin Borkar and Shekhar Y. Borkar},
year = {2008},
journal = {IEEE Journal of Solid-State Circuits},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {43},
number = {1},
pages = {29--41},
doi = {10.1109/jssc.2007.910957},
}
This record lives at https://refs.drheap.org/vangal200880tile/ and will keep doing so.