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A Formalisation of the VHDL Simulation Cycle
The work
| Authors | John P. Van Tassel |
|---|---|
| Editors | |
| Type | incollection |
| Year | 1993 |
| Citekey | vantassel1993formalisation |
Where it appeared
| Published in | Higher Order Logic Theorem Proving and its Applications |
|---|---|
| Publisher | Elsevier |
| Pages | 359--374 |
Identifiers
| DOI | 10.1016/b978-0-444-89880-7.50029-2 |
|---|---|
| ISBN | 978-0-444-89880-7 |
Access
| Landing page | https://doi.org/10.1016/b978-0-444-89880-7.50029-2 |
|---|
How it got here
| How it got here | agent via crossref |
|---|---|
| Added | 2026-10-25 06:43 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Filed under
Cite it as
@incollection{vantassel1993formalisation,
title = {A Formalisation of the VHDL Simulation Cycle},
author = {John P. Van Tassel},
year = {1993},
booktitle = {Higher Order Logic Theorem Proving and its Applications},
publisher = {Elsevier},
pages = {359--374},
isbn = {978-0-444-89880-7},
doi = {10.1016/b978-0-444-89880-7.50029-2},
}
This record lives at https://refs.drheap.org/vantassel1993formalisation/ and will keep doing so.