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Formal verification of timed systems: a survey and perspective
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Abstract
An overview of the current state of the art of formal verification of real-time systems is presented. We discuss commonly accepted models, specification languages, verification frameworks, state-space representation schemes, state-space construction procedures, reduction techniques, pioneering tools, and finally some new related issues. We also make a few comments according to our experience with verification tool design and implementation.
@article{wang2004formal,
title = {Formal verification of timed systems: a survey and perspective},
author = {Farn Wang},
year = {2004},
journal = {Proceedings of the IEEE},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {92},
number = {8},
pages = {1283--1305},
doi = {10.1109/jproc.2004.831197},
}