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Abstract
In present design automation systems, the standard approach that is taken to verify the correctness of proposed logic designs is that of simulation. However, due to several difficulties that arise as simulation is applied to more complex systems, designers have searched for other techniques to at least augment this traditional approach. The purpose of this paper is to briefly describe a research project to develop a formal design verification system using the Argonne Automated Reasoning Assistant (AURA). Some results of this investigation are presented, together with a discussion of some of the problems that have been encountered and plans for future work.
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Cite it as
@misc{wojcik1983formal,
title = {Formal Design Verification of Digital Systems},
author = {Anthony S. Wojcik},
year = {1983},
journal = {Proceedings - ACM IEEE Design Automation Conference},
publisher = {Association for Computing Machinery},
pages = {228--234},
doi = {10.1109/dac.1983.1585653},
}