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A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm

The work

AuthorsChia-Tsun Wu; Wen-Chung Shen; Wei Juan Wang; An-Yeu Andy Wu
Editors
Typearticle
Year2010
Citekeywu2010twocycle

Where it appeared

Published inIEEE Transactions on Circuits & Systems II Express Briefs
PublisherInstitute of Electrical and Electronics Engineers
Volume57
Issue6
Pages430--434

From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.

Abstract

This brief presents a frequency estimation algorithm (FEA) for an all-digital phase-locked loop (ADPLL) instead of the traditional binary frequency-searching algorithm. Based on the proposed FEA and a new fast-lock scheme, a fast-lock engine is designed to improve the lock-in time of an ADPLL design with two referenced clock cycles. An implementation of the proposed ADPLL design is realized by utilizing United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS technology with a core area of 300 × 250 μm2, consisting of an acceptable input reference clock ranging from 220 kHz to 8 MHz. The ADPLL design has a frequency range of 28-446 MHz with an 8.8-ps digitally controlled oscillator resolution. Moreover, the peak-to-peak jitter of the ADPLL achieves 70 ps, respectively.

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Added2026-10-27 18:52 UTC
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Cite it as

@article{wu2010twocycle,
  title        = {A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm},
  author       = {Chia-Tsun Wu and Wen-Chung Shen and Wei Juan Wang and An-Yeu Andy Wu},
  year         = {2010},
  journal      = {IEEE Transactions on Circuits \& Systems II Express Briefs},
  publisher    = {Institute of Electrical and Electronics Engineers},
  volume       = {57},
  number       = {6},
  pages        = {430--434},
  doi          = {10.1109/tcsii.2010.2048358},
}

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