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Abstract
According to Moore's Law, number of transistors on chip doubles in every next two years, So the complexity of the circuit increases. So it needs to be careful in designing and verification. Register Transfer Level (RTL) designing and its verification is also most important part of circuit design. The intent behind verification is to check that design meets all system specification and requirements or not. It is important to verify RTL before simulation and synthesis the design because It save clock cycle and time of simulation. This paper is focused on the RTL verification tool, Such as HAL linting and Spyglass RTL signoff tool. This type of RTL verification is used to find bugs and error in design before synthesis. It is easy to debug RTL design and pinpoint the problem and their solution. It is important to identify design issues as early as possible before synthesis RTL design.
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Cite it as
@misc{yadav2020study,
title = {Study and Analysis of RTL Verification Tool},
author = {Akhilesh Yadav and Poonam Jindal and Devaraju Basappa},
year = {2020},
pages = {1--6},
doi = {10.1109/sces50439.2020.9236747},
}