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Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism
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Abstract
Secure circuits are prone to a wide range of physical attacks. Among those are fault attacks based on modifying the circuit environment in order to change its behaviour or to induce faults into its computations. There are many common means used to inject such faults: laser shots, electromagnetic pulses, overclocking, chip underpowering, temperature increase, etc. In this paper we study the effect of negative power supply glitches on a FPGA. The obtained faults were compared to faults injected by clock glitches. As a result, both power and clock glitch induced faults were found to be identical. Because clock glitches are related to timing constraint violations, we shall consider that both power and clock glitches share this common fault injection mechanism. We also further studied the properties of this fault injection means.
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Cite it as
@misc{zussa2013power,
title = {Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism},
author = {Loïc Zussa and Jean-Max Dutertre and Jessy Clédière and Assia Tria},
year = {2013},
journal = {IEEE International On-Line Testing Symposium (IOLTS)},
pages = {110--115},
doi = {10.1109/iolts.2013.6604060},
}