The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips
The work
| Authors | Scott Davidson; Shaolin Xie; Christopher Torng; Khalid Al-Hawai; Austin Rovinski; Tutu Ajayi; Luis Vega; Chun Lan Zhao; Ritchie Zhao; Steve X. Dai; Aporva Amarnath; Bandhav Veluri; Paul Gao; Anuj Rao; Gai Liu; Rajesh K. Gupta; Zhiru Zhang; Ronald Dreslinski; Christopher Batten; Michael Bedford Taylor |
|---|---|
| Editors | |
| Type | article |
| Year | 2018 |
| Citekey | davidson2018celerity |
Where it appeared
| Published in | IEEE Micro |
|---|---|
| Publisher | Institute of Electrical and Electronics Engineers |
| Volume | 38 |
| Issue | 2 |
| Pages | 30--41 |
Identifiers
| DOI | 10.1109/mm.2018.022071133 |
|---|---|
| OpenAlex | W2798598799 |
Access
| Landing page | https://doi.org/10.1109/mm.2018.022071133 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
Rapidly emerging workloads require rapidly developed chips. The Celerity 16-nm open-source SoC was implemented in nine months using an architectural trifecta to minimize development time: a general-purpose tier comprised of open-source Linux-capable RISC-V cores, a massively parallel tier comprised of a RISC-V tiled manycore array that can be scaled to arbitrary sizes, and a specialization tier that uses high-level synthesis (HLS) to create an algorithmic neural-network accelerator. These tiers are tied together with an efficient heterogeneous remote store programming model on top of a flexible partial global address space memory system.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-27 06:39 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@article{davidson2018celerity,
title = {The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips},
author = {Scott Davidson and Shaolin Xie and Christopher Torng and Khalid Al-Hawai and Austin Rovinski and Tutu Ajayi and Luis Vega and Chun Lan Zhao and Ritchie Zhao and Steve X. Dai and Aporva Amarnath and Bandhav Veluri and Paul Gao and Anuj Rao and Gai Liu and Rajesh K. Gupta and Zhiru Zhang and Ronald Dreslinski and Christopher Batten and Michael Bedford Taylor},
year = {2018},
journal = {IEEE Micro},
publisher = {Institute of Electrical and Electronics Engineers},
volume = {38},
number = {2},
pages = {30--41},
doi = {10.1109/mm.2018.022071133},
}
This record lives at https://refs.drheap.org/davidson2018celerity/ and will keep doing so.