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Schematic-Level and Layout-Level ESD EDA check methodology applied to smart power IC's - initialization and implementation
The work
| Authors | Eleonora Gevinti; Lorenzo Cerati; Leonardo Di Biccari; Giuseppe Ballarin; Antonio Andreini; Mauro Fragnoli; Antonio Bogani |
|---|---|
| Editors | |
| Type | misc |
| Year | 2015 |
| Citekey | gevinti2015schematiclevel |
Where it appeared
| Published in | Electrical Overstress/Electrostatic Discharge Symposium |
|---|---|
| Pages | 1--10 |
Identifiers
| DOI | 10.1109/eosesd.2015.7314770 |
|---|---|
| OpenAlex | W1950302661 |
Access
| Landing page | https://doi.org/10.1109/eosesd.2015.7314770 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
A functional methodology to fully check IC ESD network topology together with protected circuitry ESD compliance at Schematic-Level and metal interconnections at Layout-Level is developed and applied to Smart Power products. A common operational method is developed to simultaneously initialize different Schematic-Level and Layout-Level verification tools.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-24 21:26 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{gevinti2015schematiclevel,
title = {Schematic-Level and Layout-Level ESD EDA check methodology applied to smart power IC's - initialization and implementation},
author = {Eleonora Gevinti and Lorenzo Cerati and Leonardo Di Biccari and Giuseppe Ballarin and Antonio Andreini and Mauro Fragnoli and Antonio Bogani},
year = {2015},
journal = {Electrical Overstress/Electrostatic Discharge Symposium},
pages = {1--10},
doi = {10.1109/eosesd.2015.7314770},
}
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