A framework for logic-aware layout analysis
The work
| Authors | Patrick Gibson; Ziyang Lu; Fedor G. Pikus; Sridhar Srinivasan |
|---|---|
| Editors | |
| Type | misc |
| Year | 2010 |
| Citekey | gibson2010framework |
Where it appeared
| Published in | International Symposium on Quality Electronic Design (ISQED) |
|---|---|
| Pages | 171--175 |
Identifiers
| DOI | 10.1109/isqed.2010.5450415 |
|---|---|
| OpenAlex | W2123047626 |
Access
| Landing page | https://doi.org/10.1109/isqed.2010.5450415 |
|---|
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Abstract
In this paper, we explain a new EDA tool framework that extends the reach of Electrical DFM analysis across cross-domain applications by providing the ability to do layout analysis and logical analysis of the schematics in context. To demonstrate the effectiveness and the flexibility of the integrated environment this new framework provides, we show several real-time applications of layout verification based on the logic analysis of the circuit, where the logic analysis is performed by applying the correct design rules.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-24 22:12 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@misc{gibson2010framework,
title = {A framework for logic-aware layout analysis},
author = {Patrick Gibson and Ziyang Lu and Fedor G. Pikus and Sridhar Srinivasan},
year = {2010},
journal = {International Symposium on Quality Electronic Design (ISQED)},
pages = {171--175},
doi = {10.1109/isqed.2010.5450415},
}
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