Ziyang Lu

4 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

Using static voltage analysis and voltage-aware DRC to identify EOS and oxide breakdown reliability issues

Matthew Hogan and others (2013) · 2013 35th Electrical Overstress/Electrostatic Discharge Symposium (2013), 1–6.

Static low power verification at transistor level for SoC design

Jérôme Lescot and others (2012) · ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)

A framework for logic-aware layout analysis

Patrick Gibson and others (2010) · International Symposium on Quality Electronic Design (ISQED)

Hierarchical verification of chip-level ESD design rules

Ziyang Lu and others (2010) · Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010 (2010), 1–6.