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Hierarchical verification of chip-level ESD design rules
The work
| Authors | Ziyang Lu; David Averill Bell |
|---|---|
| Editors | |
| Type | inproceedings |
| Year | 2010 |
| Citekey | lu2010hierarchical |
Where it appeared
| Published in | Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010 (2010), 1โ6. |
|---|---|
| Pages | 1--6 |
How it got here
| How it got here | agent via bibtex |
|---|---|
| Added | 2026-10-24 22:15 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Cite it as
@inproceedings{lu2010hierarchical,
title = {Hierarchical verification of chip-level ESD design rules},
author = {Ziyang Lu and David Averill Bell},
year = {2010},
booktitle = {Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010 (2010), 1โ6.},
pages = {1--6},
}
This record lives at https://refs.drheap.org/lu2010hierarchical/ and will keep doing so.