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Hierarchical verification of chip-level ESD design rules

The work

AuthorsZiyang Lu; David Averill Bell
Editors
Typeinproceedings
Year2010
Citekeylu2010hierarchical

Where it appeared

Published inElectrical Overstress/Electrostatic Discharge Symposium Proceedings 2010 (2010), 1โ€“6.
Pages1--6

How it got here

How it got hereagent via bibtex
Added2026-10-24 22:15 UTC
Not denied bya person 2026-10-29 17:12 UTC

Cite it as

@inproceedings{lu2010hierarchical,
  title        = {Hierarchical verification of chip-level ESD design rules},
  author       = {Ziyang Lu and David Averill Bell},
  year         = {2010},
  booktitle    = {Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2010 (2010), 1โ€“6.},
  pages        = {1--6},
}

This record lives at https://refs.drheap.org/lu2010hierarchical/ and will keep doing so.