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Static low power verification at transistor level for SoC design
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Abstract
This paper presents a transistor-level verification flow to detect electrical overstress, static leakage and ESD-CDM issues in large low power SoC circuits. With innovative features like Spice patterns recognition and static voltage propagation by Calibre® PERC™, this approach brings significant added value to standard digital checkers that cannot capture some parts of the design in essence, such as analog IPs or third-party IPs designed outside power-intent driven flows. The results obtained on a 32nm CMOS circuit using multiple separate supplies with body biasing strategy, demonstrate the ability of this solution to cope with complex design architectures. As a matter of fact, some severe issues like hundreds of missing level shifters and weak input stages inside isolation cells were detected in few hours.
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Cite it as
@misc{lescot2012static,
title = {Static low power verification at transistor level for SoC design},
author = {Jérôme Lescot and Vincent Bligny and Dina Medhat and Didier Chollat-Namy and Ziyang Lu and Sophie Billy and Mark Hofmann},
year = {2012},
journal = {ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)},
pages = {129--134},
doi = {10.1145/2333660.2333694},
}