Dina Medhat

3 references under this name, matched as it is written. Somebody else may write under it too, and the same person may appear here spelled another way.

A comprehensive ESD verification flow at transistor level for large SoC designs

Jerome Lescot and others (2015) · IEEE

Using static voltage analysis and voltage-aware DRC to identify EOS and oxide breakdown reliability issues

Matthew Hogan and others (2013) · 2013 35th Electrical Overstress/Electrostatic Discharge Symposium (2013), 1–6.

Static low power verification at transistor level for SoC design

Jérôme Lescot and others (2012) · ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED)