The bibliographic entry was discovered and compiled by a machine, and published without a person checking it against the publication. The publication itself is the authors' own work — this badge says nothing about it.
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA
From OpenAlex, which stores abstracts as an
index of words and their positions: what is shown is rebuilt from that,
and reads fluently whether or not it is what the author wrote.
Abstract
The protection of Intellectual Property (IP) has emerged as one of the most serious areas of concern in the semiconductor industry. To address this issue, we present a method and architecture to map selective portions of a design, given as a behavioral description for High-Level Synthesis (HLS) to a high-security embedded Field-Programmable Gate Array (eFPGA). In this manner, only the end-user has access to the full functionality of the chip. Using six benchmark circuits, we show that our approach is effective. In all cases, the Time-To-Break (TTB) is so long (at least 8 million hours) that for all practical purposes the designs are secure while incurring area overheads of around 5%. Further, latencies were only slightly increased, while the computation times are under one minute.
@misc{hu2019functional,
title = {Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA},
author = {Bo Hu and Jingxiang Tian and Mustafa Shihab and Gaurav Rajavendra Reddy and William Swartz and Yiorgos Makris and Benjamin Carrión Schäfer and Carl Sechen},
year = {2019},
journal = {ACM Great Lakes Symposium on VLSI (GLSVLSI)},
pages = {171--176},
doi = {10.1145/3299874.3317992},
}