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Next generation Intel® micro-architecture (Nehalem) clocking architecture
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Abstract
This paper describes the next generation Intelregmicro-architecture (Nehalem) 45 nm IA processorpsilas core and I/O clocking architecture. Among the highlights are: configurable clocking, fastlock low-skew PLLs, high reference clock frequencies, analog supply tracking system, adaptive frequency clocking, low jitter IntelregQuickPath interconnect and IntelregQuickPath memory controller clock generation, and jitter-attenuating DLLs.
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Cite it as
@misc{kurd2008next,
title = {Next generation Intel® micro-architecture (Nehalem) clocking architecture},
author = {Nasser A. Kurd and Jonathan Douglas and Praveen Mosalikanti and Rajesh Kumar},
year = {2008},
journal = {IEEE Symposium on VLSI Circuits (VLSI-Circuits)},
pages = {62--63},
doi = {10.1109/vlsic.2008.4585952},
}