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Formal Verification of Analog Circuit Parameters across Variation Utilizing SAT
The work
| Authors | Merritt P. Miller; Forrest D. Brewer |
|---|---|
| Editors | |
| Type | misc |
| Year | 2013 |
| Citekey | miller2013formal |
Where it appeared
| Published in | Design, Automation, and Test in Europe |
|---|---|
| Pages | 1442--1447 |
Identifiers
| DOI | 10.7873/date.2013.294 |
|---|---|
| OpenAlex | W4234585396 |
Access
| Landing page | https://doi.org/10.7873/date.2013.294 |
|---|
From OpenAlex, which stores abstracts as an index of words and their positions: what is shown is rebuilt from that, and reads fluently whether or not it is what the author wrote.
Abstract
A fast technique for proving steady-state analog circuit operation constraints is described. Based on SAT, the technique is applicable to practical circuit design and modeling scenarios as it does not require algebraic device models. Despite the complexity of representing accurate transistor I/V characteristics, run-time and problem scaling behavior is excellent.
How it got here
| How it got here | agent via openalex |
|---|---|
| Added | 2026-10-24 22:16 UTC |
| Not denied by | a person 2026-10-29 17:12 UTC |
Filed under
Cite it as
@misc{miller2013formal,
title = {Formal Verification of Analog Circuit Parameters across Variation Utilizing SAT},
author = {Merritt P. Miller and Forrest D. Brewer},
year = {2013},
journal = {Design, Automation, and Test in Europe},
pages = {1442--1447},
doi = {10.7873/date.2013.294},
}
This record lives at https://refs.drheap.org/miller2013formal/ and will keep doing so.