This description was written by a machine and published without a person checking it. It is what the agent made of this grouping, and not a statement anybody has stood behind.
The switch or the curve
A subject the papers are about. The loosest grouping, and the one to reach for last.
A transistor is a switch for proof and a current-voltage curve in silicon. Works that choose between those models and pay for the choice. Membership: commits to how much device physics a correctness argument admits.
58 references
Formally Verifying Analog Neural Networks Under Process Variations Using Polynomial Zonotopes
Yasmine Abu-Haeyeh and others (2026)
Modeling Techniques for the Formal Verification of Integrated Circuits at Transistor-Level: Performance Versus Precision Tradeoffs
Oussama Oulkaid and others (2026) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · Institute of Electrical and Electronics Engineers (IEEE)
A Survey on Transistor-Level Electrical Rule Checking of Integrated Circuits
Bruno Ferres and others (2025) · ACM Transactions on Design Automation of Electronic Systems · Association for Computing Machinery (ACM)
Formal Models of Integrated Circuits for Transistor Level Electrical Verification
Oussama Oulkaid (2025)
Formal Verification of Nonlinear Analog Circuits using State Space-Based Model Order Reduction
Yasmine Abu-Haeyeh and others (2024) · International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design
A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving
Oussama Oulkaid and others (2024) · 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE) · IEEE
Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory
Bruno Ferres and others (2023)
A Composable Glitch-Aware Delay Model
Jürgen Maier and others (2021) · Proceedings of the Great Lakes Symposium on VLSI 2021 · Association for Computing Machinery
The Involution Tool for Accurate Digital Timing and Power Analysis
Daniel Öhlinger and others (2021) · Integration, the VLSI Journal · Elsevier BV
A Faithful Binary Circuit Model
Matthias Függer and others (2020) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · IEEE
Behavioral Modeling of Transistor-Level Circuits using Automatic Abstraction to Hybrid Automata
A. Tarraf and others (2019) · IEEE
Metastability-Containing Circuits
Stephan Friedrichs and others (2018) · IEEE Transactions on Computers · Institute of Electrical and Electronics Engineers (IEEE)
Unfaithful Glitch Propagation in Existing Binary Circuit Models
Matthias Függer and others (2016) · IEEE Transactions on Computers · Institute of Electrical and Electronics Engineers (IEEE)
Earth Mover's Distance as a Comparison Metric for Analog Behavior
Alexander W. Rath and others (2016) · VLSI-SoC: Design for Reliability, Security, and Low Power. 24th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) · Springer International Publishing
Experimental Validation of a Faithful Binary Circuit Model
Robert Najvirt and others (2015) · Proceedings of the 25th edition on Great Lakes Symposium on VLSI · ACM
Faithful Glitch Propagation in Binary Circuit Models
Matthias Függer and others (2014)
Transient Behavior of Distributed Algorithms and Digital Circuit Models
Thomas Nowak (2014)
Formal Verification of Analog Circuit Parameters across Variation Utilizing SAT
Merritt P. Miller and others (2013) · Design, Automation, and Test in Europe
Oscillator Verification with Probability One
Chao Yan and others (2012) · Formal Methods in Computer-Aided Design (FMCAD) · IEEE
Analog Circuit Verification by Statistical Model Checking
Ying-Chih Wang and others (2011) · 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)
Formal Verification of C-element Circuits
Chao Yan and others (2011) · IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2011)
Formal Verification of an Arbiter Circuit
Chao Yan and others (2010) · 2010 IEEE Symposium on Asynchronous Circuits and Systems · IEEE
Analog Circuit Verification: a State of an Art
O. Maler (2006) · Elsevier BV
Verification System for Transient Response of Analog Circuits Using Model Checking
T.R. Dastidar and others (2005) · Verification System for Transient Response of Analog Circuits Using Model Checking, VLSID’05
Rigorous analog verification of asynchronous circuits
K. Papadantonakis (2005)
Verity—A formal verification program for custom CMOS circuits
Andreas Kuehlmann and others (1995) · IBM Journal of Research and Development · IBM
Switch-Level Models in Multi-level VHDL Simulations
K Khordoc and others (1992) · Springer US
Formally verified synthesis of combinational CMOS circuits
David A. Basin and others (1991) · Integration, the VLSI Journal · Elsevier BV
Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis
Randal E. Bryant (1991) · International Conference on Computer-Aided Design (ICCAD '91)
Formal Verification of Memory Circuits by Switch-Level Simulation
Randal E. Bryant (1991) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A methodology for hardware verification based on logic simulation
Randal E. Bryant (1991) · Journal of the ACM · Association for Computing Machinery
Automatic and semi-automatic verification of switch-level circuits with temporal logic and binary decision diagrams
M. Fujita and others (1990) · 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers · IEEE Comput. Soc. Press
Multilevel verification of MOS circuits
D. Weise (1990) · Institute of Electrical and Electronics Engineers (IEEE)
Verification of Combinational Logic in Nuprl
David A. Basin and others (1989) · Cornell University
The notion of proof in hardware verification
Avra Cohn (1989) · Journal of Automated Reasoning · Springer Science and Business Media LLC
IRSIM: an incremental MOS switch-level simulator
A. Salz and others (1989) · Proceedings of the 1989 26th ACM/IEEE conference on Design automation conference - DAC '89 · ACM Press
A formal approach towards electrical verification of synchronous MOS circuits
I. Bolsens and others (1988) · IEEE
Formalising an integrated circuit design style in higher order logic
Inderpreet-Singh Dhingra (1988) · University of Cambridge Computer Laboratory
Reasoning about the function and timing of integrated circuits with Prolog and temporal logic
Miriam Ellen Leeser (1988) · University of Cambridge Computer Laboratory
Reasoning about the function and timing of integrated circuits with Prolog and temporal logic
M. E. Leeser (1988) · University of Cambridge Computer Laboratory
A Compositional Model of MOS Circuits
Glynn Winskel (1988) · VLSI Specification, Verification and Synthesis · Kluwer Academic Publishers
Algorithmic Aspects of Symbolic Switch Network Analysis
Randal E. Bryant (1987) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · Institute of Electrical and Electronics Engineers
Boolean Analysis of MOS Circuits
Randal E. Bryant (1987) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · Institute of Electrical and Electronics Engineers (IEEE)
Two Papers on a Symbolic Analyzer for MOS Circuits
Randal E. Bryant (1987) · Carnegie Mellon University, Computer Science Department
Formal validation of an integrated circuit design style
Inderpreet-Singh Dhingra (1987) · University of Cambridge Computer Laboratory
Formal Multilevel Hierarchical Verification of Synchronous MOS Circuits
Daniel Wayne Weise (1987) · MIT Artificial Intelligence Laboratory
Functional verification of MOS circuits
Daniel Weise (1987) · Proceedings - ACM IEEE Design Automation Conference · Association for Computing Machinery
Models and logic of MOS circuits
Glynn Winskel (1987) · Logic of Programming and Calculi of Discrete Design · Springer
Relating two models of hardware
Glynn Winskel (1987) · Category Theory and Computer Science · Springer Berlin Heidelberg
Hardware Verification using Higher-Order Logic
Albert Camilleri and others (1986) · University of Cambridge Computer Laboratory
Automatic determination of signal flow through MOS transistor networks
W.F. Clocksin and others (1986) · Elsevier BV
Models and logic of MOS circuits: Lectures for the Marktoberdorf Summerschool, August 1986
Glynn Winskel (1986) · University of Cambridge, Computer Laboratory
Symbolic Verification of MOS Circuits
Randal E. Bryant (1985) · 1985 Chapel Hill Conference on Very Large Scale Integration
A Switch-Level Model and Simulator for MOS Digital Systems
Randal E. Bryant (1983) · California Institute of Technology, Computer Science Department
MOSSIM II: A Switch Level Simulator for MOS LSI, User's Manual
Randal E. Bryant and others (1982) · California Institute of Technology, Computer Science Department
A Switch-Level Model of MOS Logic Circuits
R. E. Bryant (1981) · VLSI 81 · Academic Press
MOSSIM: A Switch-Level Simulator for MOS LSI
R.E. Bryant (1981) · 18th Design Automation Conference · IEEE
A Switch-Level Simulation Model for Integrated Logic Circuits
Randal E. Bryant (1981)