Formal Verification of an Arbiter Circuit

The work

AuthorsChao Yan; Mark Greenstreet; Jochen Eisinger
Editors
Typeinproceedings
Year2010
Citekeyyan2010formal

Where it appeared

Published in2010 IEEE Symposium on Asynchronous Circuits and Systems
PublisherIEEE
Pages165--175

Identifiers

DOI10.1109/async.2010.25

Abstract

We present the circuit-level verification of a common arbiter circuit. To perform this verification, we address three issues. First, we present a specification for the arbiter and show how this specification amounts to a set of topological constraints on trajectories of the continuous model. Second, we show that computing bounding sets for these trajectories is complicated by stiffness of the differential equation model and present novel techniques for handling stiff equations in a formal verification context. Finally, we note that while no arbiter can be guaranteed to always grant a pending request, we can show liveness in the presence of concurrent requests in an "almost surely" sense.

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Added2026-09-15 20:54 UTC
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Cite it as

@inproceedings{yan2010formal,
  title        = {Formal Verification of an Arbiter Circuit},
  author       = {Chao Yan and Mark Greenstreet and Jochen Eisinger},
  year         = {2010},
  booktitle    = {2010 IEEE Symposium on Asynchronous Circuits and Systems},
  publisher    = {IEEE},
  pages        = {165--175},
  doi          = {10.1109/async.2010.25},
}

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