Soft Embedded FPGA Fabrics: Top-down Physical Design & Applications

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Abstract

Embedded FPGA (eFPGA) fabrics are finding increased use in modern System-on-Chip (SoC) designs as their programmability can be leveraged not only to accelerate a variety of workloads but also to enable upgradability, feature addition, and security. With technology scaling, designing hard eFPGA fabrics using custom layout techniques requires extensive design time, typically months, with poor process portability and is not compatible with demanding SoC design schedules. On the other hand, soft eFPGA fabrics described in RTL and designed using standard cells can potentially speed up the eFPGA design cycle and provide effortless process portability. Design methodologies for implementing soft FPGA fabrics presented in the literature typically employ a bottom-up approach wherein individual tiles are synthesized in isolation and later stitched together to generate the large FPGA fabric. However, using a bottom-up methodology to ensure fabric-level performance targets is challenging due to the lack of a global timing view across multiple tiles spanning the FPGA fabric. Previous works address this problem with a combination of manual buffering and floorplanning. However, these additional steps introduce significant deviations from standard push-button ASIC flows and detract from the productivity gains of using a soft FPGA fabric. This work proposes a top-down design methodology, which eliminates the need for floorplanning and manual buffering by providing a global timing view of the FPGA fabric to the electronic design automation (EDA) tools. The top-down methodology is tailored for full compatibility with standard ASIC design flow to facilitate the agile physical design of soft eFPGA fabrics starting from an RTL description and timing constraints, similar to any other digital block on the SoC. To implement the top-down methodology in silicon, a soft eFPGA fabric generator was designed using Chisel, an open-source hardware construction language. The soft eFPGA fabric generator can generate the RTL and timing constraints of island-style fabrics described using the open-source VTR tool. The soft eFPGA fabric generator was used to tapeout a proof of concept 16x16 tile soft eFPGA on an industrial 16nm CMOS FinFET process with a core area of 1.74mm² and operating speeds up to 630MHz. The fabric generator was extended to support heterogeneous fabrics with custom tiles and tape-out high-performance and low-power versions of a 12x12 heterogeneous fabric, with BRAM and DSP tiles, on a 22nm FinFET process with operating speeds up to v 500MHz. The true potential of a soft eFPGA fabric comes to light when it is integrated with other designs to enable new applications that were previously difficult to realize. Two such applications were implemented to demonstrate this potential, namely hardware redaction and reconfigurable co-processor for the RISC-V CPU. Both these applications leverage the top-down methodology to integrate our soft eFPGA fabrics into typical ASIC designs. First, the idea of hardware redaction, a hardware obfuscation approach, is proposed that allows the designers to substitute security-critical IP blocks within a design with a synthesizable eFPGA fabric. This method fully conceals the logic and the routing of the critical IP and is compatible with standard ASIC flows for easy integration and process portability. eFPGA redaction was demonstrated by obfuscating the control path of a RISC-V CPU on a 22nm FinFET process. For the second application, a heterogeneous soft eFPGA fabric was integrated as a RISC-V co-processor on a 22nm SoC test chip. The soft eFPGA co-processor was connected to the RISC-V CPU using The Rocket Custom Co-processor (RoCC) and can be reconfigured to support various custom instructions.